1. Field of the Invention
The present invention relates to microelectronic integrated circuits or modules. More specifically, the invention relates to electrostatic discharge (ESD) protection of microelectronic circuits.
2. Description of the Related Art
Electrostatic discharge remains a significant cause of rejections during the manufacturing of electronic devices and remains an important issue throughout the use and lifetime of the product. The input and output pins are especially vulnerable to ESD as users attach or detach external devices, such as antennas for example, from these pins. Metal oxide semiconductors (MOS) are known to be especially susceptible to ESD that can destroy the thin oxide layer of the MOS device and irreparably damage the MOS. The bipolar junction transistor (BJT) is usually considered to be less susceptible to ESD than MOS but small heterojunction bipolar transistors (HBT), such as InGaP HBTs for example, are particularly susceptible to damage from ESD. Other structures that are especially susceptible to ESD include integrated capacitors and adjacent metal lines on the semiconductor die.
The ESD can damage or reduce the life of an electrical device by exceeding the breakdown capability of dielectrics used in the integrated circuits as described in the Actel ESD Primer White Paper, Actel Corporation, Mountain View, Calif. (March, 2004), herein incorporated by reference. The dielectrics susceptible to ESD often include the capacitor and passivation dielectrics. ESD may also damage the semiconductor layers in the active device. One common approach to reducing the damage caused by unwanted ESD provides a shunt path that directs the ESD current away from the electrical device. Another approach to reducing the damage caused by ESD is to provide a robust path around, or parallel to, a sensitive device by adding a protection circuit.
U.S. patent application publication no. US 2004/0057172 A1 published on Mar. 25, 2004, herein incorporated by reference in its entirety, discloses ESD protection circuits that provide current shunt paths to protect electrical devices.
FIG. 1 is a schematic diagram illustrating an ESD protection circuit. The circuit is comprised of two branches 106, 108 in parallel to each other between the first port 101 and the second port 102. The forward branch 106 provides a path for excess current from the first port 101 to the second port 102. The reverse branch 108 provides a path for excess current from the second port 102 to the first port 101.
In the forward branch 106, a base diode stack 120 is connected in series with a resistor 122 in a voltage divider configuration between the first and second ports 101, 102. The base of a triggering transistor 130 is connected to the voltage divider. The emitter of the triggering transistor 130 is connected to the second port 102. A collector diode stack 140 is connected between the first port 101 and the collector of the triggering transistor 130 and dissipates the bulk of the excess power through the forward branch 106 of the circuit. The base diode stack 120 is selected to set the triggering threshold of the forward branch 106. Resistor 122 is selected to keep the triggering transistor 130 off during normal operation and to adjust the switch-off time of the triggering transistor 130 during an ESD event. The collector diode stack 140 may be one or more diodes connected in series or may be one or more transistors configured as diodes connected in series.
During normal operation, the triggering transistor 130 is off thereby preventing current flow from the high voltage node 101 to the low voltage node 102. When the voltage increases above the sum of the diode junction drops in the base diode stack 120, current from the high voltage node 101 flows through the base diode stack 120 and through the resistor 122. As the current increases further, the voltage across resistor 122 turns the triggering transistor 130 on and allows current to flow through the collector diode stack.
The reverse branch 108 is similar to the forward branch 106 and comprises a reverse triggering transistor 135, a reverse collector diode stack 145 and a reverse base diode stack 125. During operation, the reverse triggering transistor 135 remains off until the voltage at the second port 102 exceeds the sum of the diode junction drops in the reverse base diode stack 125 plus the base-emitter turn-on voltage (the base-emitter diode junction drop) of the reverse triggering transistor 135. When the reverse base diode stack 125 begins conducting current, the reverse triggering transistor 135 switches on after the transistor's base-emitter voltage drop is exceeded and a current begins to flow through the reverse collector diode stack 145 from the second port 102 to the first port 101.
Although the circuit of FIG. 1 is effective at preventing damage from ESD events, the diode capacitances detrimentally affect operation at RF frequencies. Furthermore, the large part count of the circuit increases the die area required to incorporate the circuit into an RF design. Therefore, there remains a need for an effective ESD protection device capable of operating at high frequencies and requiring a smaller additional die area.